The present invention relates to a solid-state image sensor.
FIG. 8 is a block diagram illustrating a conventional solid-state camera, wherein a charge coupled device (hereafter abbreviated as CCD) is applied, comprising a CCD 91, a signal processor 97, a video processor 98, a CCD driver 92 and a timing signal generator 93.
FIG. 9 is a schematic diagram illustrating a configuration of the CCD 91, wherein an object image is focused on a sensor area (photoelectric transducer section) 100, and converted into electric charges corresponding to intensity of incident light by photo-diodes 101. Generated electric charges are transferred to vertical CCDs 102 through reading transfer gates. The vertical CCDs 102 are driven by vertical transfer pulses φV1 to φV4 and transfer the electric charges horizontal CCD 103 in order. The horizontal CCD 103 is driven by horizontal transfer pulses φH1 and φH2 and transfers the electric charges to an output amplifier 104 to be output outside, namely, to the signal processor 97 of FIG. 8. To the output amplifier 104, a reset pulse φR is supplied for resetting the output amplifier 104 from remaining charge for every pixel (photo-diode).
The signal processor 97 comprises, in general, a noise reduction circuit 94, an AGC (Auto Gain Control) circuit 95 and an A/D (Analog to Digital) converter 96.
The noise reduction circuit 94 takes charge of removing amplifier noises and reset noises among noises included iii the output signal of the CCD 91, that is, amplifier noises, shot noises and reset noises. The AGC circuit 95 amplifies and maintains signal level of the output of the noise reduction circuit 94 to a fixed level. Output of the AGC circuit 95 is converted into a digital signal of a certain bit width by the A/D converter 96 to be processed by the video processor 98. In the conventional CCD camera of FIG. 8, the video signal is output after converted into digital signal. However, analog signal may be output directly.
In the video processor 98, low-pass filtering, γ-correction, peak clipping, amplification and so on of the output of the signal processor 97 are performed for outputting a video signal to be represented on a display device.
Driving pulses φH, φR, and φV for driving the CCD 91 are supplied from the CCD driver 92. The timing signal generator 93 generates timing signals such as a CCD driving pulse signal, a clock signal, or a sample-hold pulse signal to be delivered to each of the above parts.
The above described parts, that is, the signal processor 97, the video processor 98, the CCD driver 92 and the timing signal generator 93 are heretofore provided outside the CCD 91. However, personal video movies or digital cameras are widely spread recently, and more compact and economical equipment has become earnestly desired. For the purpose, circuit scale reduction and device miniaturization are actively pursued now.
As a prior art of the circuit scale reduction and the device miniaturization, configuration of the signal processor on the same semiconductor chip with the CCD is proposed in a Japanese patent application laid open as a Provisional Publication No. 259668/'89 in order to reduce the circuit scale and the cost as well of the solid-state camera.
FIG. 10 is a block diagram illustrating a solid-state camera of the prior art having a CCD 111 wherein a signal processor (frequency divider) 112 is included, and its peripheral circuits consisting of a vertical driver 113, horizontal driver 114, a generator of clock pulses and synchronous signals (hereafter abbreviated as SSCG) 117, a sub-carrier generator 118 and a video processor 119.
The solid-state camera of FIG. 10 operates as follows.
A clock pulse generator section (abbreviated as CG) 115 of the SSCG 117 generates CCD driving pulses (φV, φH and φR) to be supplied to the vertical driver 113 and the horizontal driver 114. The vertical driver 113 and the horizontal driver 114 supply the CCD driving pulses after voltage-amplified. The frequency divider 112 configured on the CCD 111 generates a horizontal synchronous signal HD according to a reset pulse φR of the CCD driving pulses, which is returned to a synchronous signal generator section (abbreviated as SSG) 116 of the SSCG 117. The sub-carrier generator 118 generates at color sub-carrier signal Fsc to be supplied to the video processor 119. The video processor 119 generates a video signal to be output from output of the CCD 111 by performing necessary processing ill the same way with the video processor 98 of FIG. 8.
As above described, a noise reduction is intended in the prior art by providing the frequency divider 112 separately from the SSCG 117 in order to prevent the CCD driving pulses to be affected from noises derived from the frequency divider 112, and a miniaturization of the equipment is realized as well by configuring the frequency divider 112 on the CCD 111.
Another prior art is disclosed in a Japanese patent application laid open as a Provisional Publication No. 184978/'86 and that of Provisional Publication No. 186080, wherein the A/D converter is configured on the CCD for the equipment miniaturization and the cost reduction.
FIG. 11 is a circuit configuration illustrating the A/D converter designed on the CCD described in the Provisional Publication No. 186080/'87.
Referring to FIG. 11, numerals 121 and 122 denote transfer electrodes of a charge coupled device each driven with each of transfer pulses φ1 and φ2. Between each pair of the transfer electrodes 121 and 122, floating electrodes 123 to 125 are inserted. The charge coupled device, a drain electrode 126 being provided for absorbing signal electrons at an end thereof, operates as a tapped delay line 127 halving tap electrodes charge-coupled therewith. Therefore, signal electrons transferred from the other end in a direction indicated by an allow 128 are transferred in the delay line 127 in order, and at the same time, they are detected nondestructively by the floating electrodes 123 to 125 each connected to an input terminal of each of analog comparators 129 to 131.
To another input terminal of each of the analog comparators 129 to 131, each of reference voltages obtained by dividing a main reference voltage with resisters 132 to 135 of the same resistance is supplied. That is, when potential of the maim reference voltage supplied to a terminal 136 is VR, potentials 3VR/4, VR/2 and VR/4 are impressed to the analog comparators 129 to 131, respectively.
Representing signal potential detected by the floating electrode 123 by VS, output C1 of the analog comparator 129 becomes at logic ‘1’ (high level) when VS>3VR/4, and otherwise at logic ‘0’ (low level). Other analog comparators 130 and 131 operate in the same way except for difference of the reference voltage VR/2 or VR/4. Therefore, logical outputs C1 to C3 of the analog comparators 129 to 131 are obtained as represented by following Table 1 according to value of the signal potential VS.
TABLE 1Comparative OutputEncoder OutputConditionC1C2C3D1D2  VS > 3VR/4111113VR/4 > VS > VR/201110 VR/2 > VS > VR/400101 VR/4 > VS00000
That is, the outputs C1, C2 and C3 become all at logic ‘1’ when VS>3VR/4, the outputs C2 and C3 being at logic ‘1’ when 3VR/4>VS>VR/2, only the output C3 at logic ‘1’ when VR/2>VS>VR/4 and none at logic ‘1’ when VR/4>VS.
Each of the digital outputs C1 to C3 is then delayed through each of digital shifts registers 137 to 139 corresponding to detection timing of the same signal electrons of the floating electrode 123 to 125 delayed in the order by a clock cycle. By delaying each of the digital outputs C1, C2 and C3 for 3, 2 and 1 clock cycles by the digital shift registers driven by the same clock signal with that driving the delay line 127, the transfer delays are compensated. Thus, the digital outputs C1 to C3 of the same signal electrons are input to an encoder 140 ranged at the same timing, and converted into a binary code of two bits D1 and D2, as listed in Table 1.
Besides these prior arts, some examples are disclosed also in Japanese patent applications laid open as Provisional Publications No. 32776/'96 and No. 154980/'87. In the former document, a RAM (Read Only Memory) is configured on a CCD together with an A/D converter, and aln A/D converter is provided on the same semiconductor chip with a MOS type image sensor in the latter document.
However, there are following problems in these prior arts.
The first problem is that only a part of peripheral circuits is configured on the same semiconductor chip of the solid-state image sensor in every of the prior arts. Therefore, field adjustment of timing pulse phases or signal balance with external circuits outside the semiconductor chip has been inevitable for eliminating pulse delay differences, dulling of wave forms or ringing interferences caused by performance dispersion of active or passive elements of the external circuits or by wiring arrangement connecting them.
The second problem is that the miniaturization effect of the equipment is limited even when a part of peripheral circuits is configured on-chip. For replying to severe market requirement for the miniaturization, main part of the peripheral circuits should be configured together with the solid-state image sensor.
The third problem is that noises are susceptible to be mingled in the output signal of the CCD, even when the frequency divider is configured on the solid-state image sensor chip as described in the above Provisional Publication No. 259668/'89. The reason is that a long wiring is left needed for the high-impedance output signal of the CCD which is supplied to external circuit directly without signal processing. This makes noise performance easily dependent of length or path of wirings or arrangement of equipment parts.